The present invention relates to a BIMOS logic gate.
In recent years, considerable attention has been paid to a BIMOS logic gate using MOS and bipolar transistors. FIG. 1 shows a BIMOS logic gate as a related art. An input terminal 1 is connected to gates of PMOS transistors 2a and 2b and NMOS transistors 3a and 3b which construct a complementary type logic circuit. An output of the complementary type logic circuit is connected to a base of a first bipolar transistor 4 whose emitter is connected to an output terminal 5 and which functions as a buffer when the output rises. When the output trails, a second bipolar transistor 6 whose emitter and collector is connected to the preground and output terminal 5 respectively discharges the stored charges at the output terminal 5. NMOS transistors 7a and 7b are provided to control the conduction between base and collector of the second bipolar transistor 6 by the logic state of the input terminal 1. Transistors 7a and 7b are connected between the base and collector of the transistor 6. A current which flows through the NMOS transistors 7a and 7b is injected to the base of the second bipolar transistor and is amplified to a large collector current due to the current amplifying function of the bipolar transistor, thereby realizing the steep trailing of the output voltage. An NMOS transistor 8 is provided to cut off the second bipolar transistor 6 when the output level of the output terminal 5 is set to "1". Reference numeral 9 denotes a power source. In the above construction, to construct the complementary type logic circuit, the NMOS transistors 3a and 3b are of the enhancement type and the NMOS transistors 7a and 7b are also of the enhancement type in accordance with those transistors.
As compared with the ordinary complementary type logic circuit using only MOS transistors, the foregoing type of circuit has features such that the dependence of the logic delay time on the load capacitor is small and the speed is high due to the buffer operation of the bipolar transistor.
However, as shown in H MOMOSE, "0.5 MICRON MICMOS TECHNOLOGY", IEDM (International Electron Devices Meeting) 87, the related art circuit as shown in FIG. 1 has a problem such that when the power source voltage drops, the delay time rapidly becomes large. Such a problem is an extremely significant subject when future fine MOS transistors are used.